FPGA Design Engineer

Saffron Walden
1 year ago
Applications closed

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FPGA Design Engineer

Saffron Walden, UK | Permanent | £50k - £70k D.O.E

The company

Our client is an electronics and technology SME operating in the field of aerospace, defence and government, involved in the design and sale of electronic-scanning ground radar systems.

The Role

You will be supporting a major product update to extend the company’s existing offering of radars, as they introduce enhanced performance and new capabilities that includes updates to FPGAs and other programmable logic across their entire radar family.

Key responsibilities:

• Take the lead on DSP system design and architecture.

• Design, develop and verify FPGA code (VHDL or Verilog), using Xilinx design tools.

• Design software for test and verification of FPGA code.

• Take the lead on field trials of signal processing performance.

• Generate design documentation for communication and dissemination across the engineering team.

Qualifications, experience and skills

• Engineering or other technical degree (or equivalent combination of experience and education).

• Development experience using Xilinx design tools such as Vivado, targeted at Zynq MPSoC or similar.

• Experience of implementing signal processing algorithms with high-speed I/O in FPGA.

• Understanding of the design of high-speed digital circuits for real-time systems.

• Experience of design verification by both simulation (SystemVerilog or similar) and hardware testing.

• Experience of software design using C/C++, Python, or Rust.

• Proficient using test equipment such as oscilloscopes, spectrum analysers, signal generators, etc.

• Excellent interpersonal and written communication skills to allow efficient hybrid office/home collaborative working.

Additional desirable requirements

• Knowledge of radar, sonar, or similar sensor systems.

• Understanding of radar signal processing techniques.

• Embedded Linux C/C++ development.

• Familiarity with Yocto and/or Petalinux build systems.

• Familiarity with Xilinx HLS

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